Professional Development Courses

ESTC 2022 offers high-level Professional Development Courses on Tuesday, September 13th, in the morning. Don't miss this excellent opportunity to benefit from the knowledge of international electronic packaging expert.

Attending a PDC is possible for an additional fee. This fee includes course materials, coffee break and lunch after the PDC.

Please select the course you are interested in during your regular conference registration.

Content

In this course, we will explore the key global trends impacting the Electronics Manufacturing and PCB Assembly Industry and the challenges that they bring to manufacturers – including the global shortage in components, dramatic increase in PCB complexity, significant increase in New Product Introductions (NPIs) and Product Revisions and decrease in lot sizes up to “lot-size-one”. We will demonstrate why digitalization of the electronics factory is the most effective solution to many of these challenges and why building a holistic end-to-end digitalization strategy can provide the most significant return-on-investment (ROI). 

The PDC will also cover the topics, which have been described in the following e-book, white papers and webinar sessions:

• Siemens_ebook_Oren Manor_Advanced-Manufacturing-In-the-Digital-Age-2nd-edition_tcm27-97004.pdf
• Siemens-SW-(Mike Santarini)-Digital-transformation-How-Siemens-EDA-helps-you-engineer-a-smarter-future-faster-83731-WP-C5.pdf
• Siemens-PLM-Smart-manufacturing-for-electronics-WhitePaper_tcm27-57766.pdf
• Siemens-SW-A-comprehensive-digital-twin-for-PCB-assembly_WhitePaper_tcm27-64886.pdf
• Digital twin webinar series _ Jay Gorajia.docx
• Siemens-SW-Driving-engineering-for-vehicle-electrification-WhitePaper_tcm27-93397.pdf

Content

After scale-up and high-volume manufacture of simple single-chip Fan-Out Wafer Level Packaging (FO-WLP) solutions by companies like Qualcomm and Infineon, now many premier semiconductor companies and OEM’s have adopted Advanced Fan-Out structures including Apple, AMD, MediaTek, HiSilicon, and Xilinx. These companies are leveraging foundry technologies like InFO offered by TSMC as well as OSAT solutions from ASE, Amkor, SPIL, PTI, DECA, and Nepes. This course will cover the advantages of FO-WLP, potential application spaces, advanced package structures available in the industry, technology roadmaps, and benchmarking. The challenges of moving from 300mm FO-WLP to panel will also be discussed.

Course Outline:

• Definitions and Advantages
• Advanced Applications
• Package Structures including Advanced FO technologies
• Technology Roadmap
• Panel Challenges
• Benchmarking

Content

Fan-out wafer/panel-level packaging has been getting lots of tractions since TSMC used their integrated fan-out to package the application processor chipset for the iPhone 7. In this lecture, the following topics will be presented and discussed. Emphasis is placed on the fundamentals and latest developments of these areas in the past few years. Their future trends will also be explored. Chiplet is a chip design method and heterogeneous integration (HI) is a chip packaging method. HI uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (either side-by-side, stacked, or both) with different sizes and functions, and from different fabless design houses, foundries, wafer sizes, and feature sizes into a system or subsystem on a common package substrate. These chips can be any kind of devices and don’t have to be chiplets. On the other hand, for chiplets, they have to use the heterogeneous integration to package them. For the next few years, we will see more implementations of a higher level of chiplet designs and HI packaging, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in chiplet design and HI packaging will be presented.

Course Outline:

1. Formation of FOWLP: (a) Chip-First (Die Face-Down), (b) Chip-First (Die Face-Up), and (c) Chip-Last (or RDL-First)
2. Fabrication of Redistribution Layers (RDLs): (a) Polymer and ECD Cu + Etching, (b) PECVD and Cu Damascene + CMP, (c) Hybrid RDLs, and (d) Laser drill + LDI + PCB Cu-plating + Etching
3. Formation of FOPLP: (a) Chip-First (Die Face-Down), (b) Chip-First (Die Face-Up), and (c) Chip-Last (or RDL-First)
4. TSMC InFO: (a) InFO-PoP, and (b) InFO_AiP Driven by 5G mmWave
5. Samsung PLP: (a) PoP for Smart Watches and (b) SiP SbS for Smartphones
6. Warpages: (a) Warpage Types and (b) Allowable of Warpages
7. Reliability of FOWLP and FOPLP: (a) Thermal-Cycling Test, (b) Thermal-Cycling Simulations, (c) Drop Test, and (d) Drop Simulations
8. Examples: (a) Chip-First Panel-Level Fan-Out Packaging of Mini-LED for RGB-Display, (b) Chip-Last Panel-Level Fan-Out Packaging of Application Processor Chipset, (c) 2.3D IC Integration with Chip-First Fan-Out RDL-Interposers, and (d) 2.3D IC Integration with Chip-Last Fan-Out RDL-Interposers
9. Chiplet Design and HI Packaging vs. System-on-Chip (SoC)
10. Advantages and Disadvantages of Chiplet Design and HI Packaging
11. Examples: (a) Xilinx Chiplet Design and HI Packaging (Virtex), (b) AMD Chiplet Design and HI Packaging (EPYZ and RYZEN), (c) Intel Chiplet Design and HI Packaging (FOVEROS, FOVEROS Direct, and Ponte Vecchio), and (d) TSMC Chiplet Design and HI Packaging (SoIC + CoWoS and SoIC + InFO PoP)
12. Chiplets Lateral Interconnects (Bridges): (a) Intel’s EMIB, (b) IBM’s DBHi, (c) Applied Materials’ Bridge Embedded in Fan-Out EMC, (d) SPIL’s FO-EB, (e) TSMC’s LSI, (f) ASE’s sFOCoS, (g) IME’s EFI, (h) Amkor’s S-Connect Fan-Out Interposer, and (i) UCIe
13. Chiplet Design and HI Packaging on Organic Substrates (SiP): many examples
14. Chiplet Design and HI Packaging on Silicon Substrates (TSV-Interposers): many examples: (a) Leti, (b) IME, (c) HKUST, (d) ITRI, (e) Xilinx/TSMC, (f) Altera/TSMC, (g) NVidia/TSMC, (h) AMD/UMC, (i) AMD’s Active Interposer, (j) Intel’s FOVEROS Direct and Ponte Vecchio, (k) TSMC’s SoIC, and (l) Samsung’s X-Cube and H-Cube
15. Chiplet Design and HI Packaging on Fan-Out RDL Substrate for High Performance Applications: many examples: (a) STATSChipPac’s FOFC-eWLB, (b) ASE’s FOCoS (Chip-First), (c) MediaTek’s FO-RDLs, (d) TSMC’s InFO_oS and InFO_MS, (e) Samsung’s Si-Less RDL Interposer, (f) TSMC’s RDL-Interposer, (g) ASE’s FOCoS (Chip-Last), (h) Shinko’s Organic RDL-Interposer, and (i) Unimicron’s Hybrid Substrate
16. Assembly Technologies for Chiplet Design and HI Packaging: (a) SMT, (b) Solder Bumped Flip Chip, (c) CoW, (d) WoW, (e) TCB, and (f) Bumpless Cu-Cu Hybrid Bonding
17. Summary

Who Should Attend?

If you (students, engineers, and managers) are involved with any aspect of the electronics industry, you should attend this course. It is equally suited for R&D professionals and scientists. The lectures are based on the publications by many distinguish authors and the books (by the lecturer) such as Fan-Out Wafer-Level Packaging (Springer, 2018), Heterogeneous Integration (Springer, 2019), and Semiconductor Advanced Packaging (Springer, 2021). Each attendee will receive more than 300 pages of lecture notes.

Content

The production, design, assembly, and accelerated testing of additively printed flexible hybrid electronics for use in several cutting-edge fields will be discussed in this course. We will talk about the manufacturing procedures for flexible hybrid electronics that are made additively. Flexible hybrid electronics creates opportunities for the creation of stretchable, flexible, and foldable form-factors in electronics applications, which are not yet conceivable with the usage of rigid electronics technology.  Flexible electronics may experience strain magnitudes in the range of 50 to 150 percent when used normally. When compared to rigid electronics, the integration methods and semiconductor package layouts for flexible hybrid electronics might be very different. Thin-chip integration, flexible encapsulation, compliant interconnects, and stretchable inks for metallization traces are all necessary for the production of thin electronic structures.  It is now feasible to use a multitude of additive manufacturing techniques for the production and assembly of flexible hybrid electronics. In order to develop robust process parameters that will enable acceptable levels of yields in high-volume manufacturing, processes for handling, pick-and-place operations of thin silicon, and compliant interposers through interconnection processes like reflow, call for an understanding of the deformation and warpage processes. Flexible electronics may also require different testing, validation, and quality assurance procedures to assure reliability and survivability under exposure to prolonged harsh environmental working conditions